Founding Compiler Engineer

Founding AI Compiler Engineer - $750k+ - EquityWe are partnering with an early-stage AI hardware company developing a new accelerator architecture and the complete software stack required to make it programmable.They are seeking a Founding AI Compiler Engineer to take technical ownership of the compiler from its earliest architectural decisions through to production deployment on custom silicon.This is an opportunity for an experienced compiler engineer to become the technical foundation of a new organisation, remain deeply hands-on and ultimately help build the team around them.What you’ll doOwn the technical architecture and development of a new AI compilerBuild the initial compiler pipeline from ML frameworks and graph representations through intermediate representations to executable codeDetermine where LLVM, MLIR or other compiler infrastructure should be adopted, extended or replacedTranslate representative AI workloads into compiler and hardware requirementsCollaborate with architecture teams on ISA design, instruction selection, register usage, memory systems and synchronizationEnable initial models and workloads on pre-silicon simulators before supporting first-silicon bring-upInvestigate compiler-generated performance at the graph, kernel and instruction levelsDefine engineering standards and a technical roadmap for the compiler stackHelp recruit and mentor the compiler team as the company growsEngage with early customers and application teams to understand programmability and workload requirementsWhat we’re looking forSignificant experience building production compilers, preferably for GPUs, AI accelerators, DSPs, CPUs or other parallel architecturesDeep knowledge of LLVM, MLIR or comparable compiler infrastructureExperience working across several stages of a compiler rather than contributing exclusively to an isolated passStrong understanding of intermediate representations, lowering, code generation and compiler optimisationExperience developing hardware-aware transformations such as fusion, tiling, vectorisation, scheduling, memory planning or layout optimisationUnderstanding of parallel-compute architectures and the relationship between compiler decisions and hardware performanceAbility to operate effectively in an early-stage environment with incomplete specifications and evolving hardware