Principal Researcher for Novel DRAM

Key Responsibilities

1. Si-based 3D DRAM: 1) Novel Metals & Interconnect Strategy:Lead the research and integration of advanced low-resistivity conductive materials for sub-10nm metal line and interconnect applications.Focus on materials screening, physical property optimization (e.g. thermal stability and work function engineering), process optimization, and HVM readiness evaluation and preparation.2) Advanced Junction Formation:Define the process for ultra-scaled junction formation.Develop low-thermal-budget process and technology to achieve precise doping profiles and activation, ensuring optimal device performance in HAR 3D structures.Develop novel characterization technologies for precise junction profile measurements in complex 3D structures.3) 3D Architecture & Silicide Integration:Overcome challenges in high aspect ratio structures.Develop robust n-type silicide processes for complex 3D geometries, ensuring low contact/barrier resistance, high step coverage, high thermal stability, and future scalability in deep trench/via applications.2. DRAM with novel channel oxide materials:Development of novel DRAM array memory architecture.Research and development of novel DRAM transistor channel materials.Novel device design and performance optimization.Research and development of key processes and process integration technologies.Development of TEG design, peripheral circuit design, and structural/electrical testing solutions.Materials, process, and device simulation.Required Qualifications:Education: Master's degree or above (PhD preferred).Major: Physics, material science & engineering, chemistry.Other Requirements:8+ years of DRAM memory development experience, including at least 5 years as architecture or key technology lead.Familiar with TLC/QLC/PLC multi-bit memory mechanisms and their challenges to read/write algorithms, ECC, and wear leveling.Excellent systems thinking and cross-domain integration capabilities, able to efficiently coordinate circuit, device, firmware, verification, testing, and product teams.Excellent technical documentation writing and technical decision-making communication skills.In-depth understanding of the ECC architecture (BCH/LDPC) and DRAM controller collaboration mechanism is preferred.Familiarity with the impact of reliability modeling under advanced processes (such as TDDB, HCI, RTN) on the architecture.Publication of DRAM-related papers at international conferences (such as ISSCC, VLSI, IMW) is a plus.Work Location: SingaporeAbout UsBrightecs Innovation Pte. Ltd. (BIP) is a private limited company incorporated in Singapore, founded in September 2025. As a newly established, technology-oriented startup, our core business is currently focused on silicon IP for intelligent computing.At the core of our operations is our R&D center, Superam Academy of Semiconductor Research (Superam), a fabless chip research institution also based in Singapore. It specializes in high-end semiconductor IP services, offering diverse IP solutions and standard cell libraries for advanced CMOS technologies by employing Design-Technology-Co-Optimization (DTCO) technology. we enable our customers to achieve full optimization of Power, Performance, and Area (PPA) when designing on foundries' unique processes.As our business continues to grow, BIP is committed to expanding its capabilities and scope into broader areas of technology innovation. We invite talented professionals to join us on this exciting journey. For more company information, please visit www.bipsuperam.com.Why Join BIPAt BIP, you will be a founding contributor to something extraordinary. We are a young, passionate team driven by curiosity and a shared ambition to push the boundaries of technology. Here, your ideas matter, your contributions are visible, and your growth is limited only by your ambition. As we expand into new frontiers, we invite you to grow with us, take on challenges that inspire you, and help shape the future from day one. Ready to make a real impact? Apply now and build the future with us.