Senior/Principal Researcher – NPU / CPU Micro-architecture / Agentic AI

Senior/Principal Researcher – NPU / CPU Micro-architecture / Agentic AIWe are currently partnered with a highly technical research organisation working on next-generation processor architectures for AI workloads. This role focuses on research and prototyping across NPU core micro-architecture, memory systems, and CPU architectures designed for agentic AI workloads, including rapid context switching, bursty compute, tool calling, agent-logic scheduling, and context management.Key responsibilitiesResearch next-generation NPU core micro-architecture across frontend, execution, backend, and memory-system components.Investigate frontend mechanisms including branch prediction, BTBs, and instruction prefetching.Explore register file organisation, issue and wake-up logic, and scalar, vector, and tensor functional units.Investigate NPU backend structures including TLBs, L1 caches, and scratchpads.Research cache hierarchies and memory systems capable of sustaining high bandwidth and low latency for compute units.Design and prototype CPU architectures tailored to agentic AI workloads, including tool calling, agent-logic scheduling, and context management.Key requirementsPhD in Computer Science, Electrical Engineering, or a related field.Strong background in Computer Architecture and Micro-architecture.Creativity and ability to develop innovative technologies.Research experience and/or strong knowledge in one or more of the following: Computer Architecture and Micro-architecture of modern Intel, ARM, or AMD CPUs, Nvidia GPUs, or Google TPUs.Computer architecture simulators including Gem5, ChampSim, Sniper, ZSim, or QFlex.Vector and matrix extensions including ARM SVE/SME or Intel SSE/AVX/AMX.GPU programming models, including CUDA kernels and PTX/SASS instructions.KeywordsNPU / Neural Processing Unit / CPU / Agentic AI / Agentic CPU / Computer Architecture / Micro-architecture / Core Micro-architecture / Branch Prediction / BTB / Instruction Prefetching / Register Files / Issue Logic / Wake-up Logic / Scalar Functional Units / Vector Functional Units / Tensor Units / TLB / L1 Cache / Scratchpads / Cache Hierarchy / Memory Systems / High Bandwidth / Low Latency / Context Switching / Bursty Compute / Thread-level Concurrency / SMT / 2-way SMT / Tool Calling / Agent-logic Scheduling / Context Management / Gem5 / ChampSim / Sniper / ZSim / QFlex / ARM SVE / ARM SME / Intel SSE / Intel AVX / Intel AMX / CUDA / PTX / SASS / GPU Programming / Micro-architecture Characterisation / Profiling / Bottleneck Analysis / Performance Monitoring Units / PMUs / Intel CPUs / ARM CPUs / AMD CPUs / Nvidia GPUs / Google TPUs / Computer Architecture Research / Processor Architecture / Research Prototyping / ASPLOS / ISCA / MICRO / HPCABy applying to this role, you understand that we may collect your personal data and process it in line with our privacy policy.https://eu-recruit.com/wp-content/uploads/2025/01/European-Tech-Recruit-Privacy-Notice-2025.pdf